The fact that AMD already feverishly on the successor to Deneb, screwed Thuban & Co., should all art enthusiasts already be clear. Today, the colleagues of the X-bit labs new information coming to light have promoted Bulldozer architecture. The new chips will have a much improved performance than all currently available x86 compatible processors, if the information so far have found their way onto the internet, is to be believed.
So just to benefit from the redesign of the cache, and is now up to 77% of larger than before. Thus, the top version with 8 cores now of 2 megabytes per module (a module containing two nuclei) as a shared L2 cache (shared L2 cache) can benefit, what the performance of the single-threaded applications, so applications that (may) use only one core should increase. Together with the 8-megabyte L3 cache bulldozers are a total of 16 MB of cache available to current Thuban offer only 9 MB of total cache. Also, the HyperTransport bus to be drilled to version 3.1, which will offer even faster connections and more efficient management, which is to manage the many units and caches are urgently needed. Although this was a new message, the shot his way around the world, but this image must be viewed with caution because, inter alia, be smaller than those above the lower modules - a modular system, however, should all be equal and the same units are home.
Whether and how big turn out the difference in performance by the next generation of AMD processors, can still hardly anyone to estimate but it is always exciting.
So just to benefit from the redesign of the cache, and is now up to 77% of larger than before. Thus, the top version with 8 cores now of 2 megabytes per module (a module containing two nuclei) as a shared L2 cache (shared L2 cache) can benefit, what the performance of the single-threaded applications, so applications that (may) use only one core should increase. Together with the 8-megabyte L3 cache bulldozers are a total of 16 MB of cache available to current Thuban offer only 9 MB of total cache. Also, the HyperTransport bus to be drilled to version 3.1, which will offer even faster connections and more efficient management, which is to manage the many units and caches are urgently needed. Although this was a new message, the shot his way around the world, but this image must be viewed with caution because, inter alia, be smaller than those above the lower modules - a modular system, however, should all be equal and the same units are home.
Whether and how big turn out the difference in performance by the next generation of AMD processors, can still hardly anyone to estimate but it is always exciting.